1. Field of the Invention
The present invention relates to the design of circuits. More specifically, the present invention relates to automated tools for predicting the performance of circuitry.
2. Background Information
As very large scale integrated circuits (VLSI) designs have grown increasingly complex, the modeling of the circuit has shifted to the new high-level hardware description languages or HDL's. One example of an HDL is known as "VHDL" or VHSIC Hardware Specification Language IEEE Standard 1076-1987). See, Perry, VHDL, (Second Ed. 1993). HDL's typically use a modeling scheme known as a register transfer level (RTL) description which is an abstraction used in chip design to model the various flows of paths through a circuit. Although such modeling techniques are very powerful tools for designing modem circuits, such as integrated circuits, the HDL or RTL design neglects to take into account very large propagation delays for generating individual signals in the circuit. Therefore, after a complete design of a functioning HDL model, the HDL designer must later provide performance optimization to insure generation of the signals at the most appropriate intervals. Such signal optimization typically is performed after design of the HDL model, and is typically solved using manual redesigns of the block in question. As a results, performance problems, such as long propagation delays in generating certain signals, are discovered later after the logical synthesis of the blocks in the circuit, and typically entail a redesign of the RTL and even higher levels of the design. This results in costly circuit and layout redesigns, which is a large waste of time and effort.
Therefore, what is needed is the estimation of delays of signals due to propagation delays of other signals upon which those signals are dependent, at early stages of the design. Moreover, it is important that these estimations be as fast as possible and enable fast turnaround times for the HDL developer.